In an image pickup apparatus such as a video camera, after an image signal acquired with an image pickup device such as a Charge Coupled Device (CCD) image sensor has been subjected to signal processing, the resulting signal is recorded in a storage medium or displayed in the form of an image on a display apparatus. An analog signal processing circuit and a digital signal processing circuit execute the signal processing. In particular, within the digital signal processing circuit, a Digital Signal Processor (DSP) executes the image processing while referring to or updating various control variables which are set in a register.
For example, the DSP is constituted by a DSP block for executing image signal processing, and a register block including a plurality of registers in which control variables can be set from the outside. The DSP block stores variables representing an image state, etc., such as an exposure state, which are obtained by means of the image signal processing in the registers, and executes the image signal processing for a next picture by using those variables. Also, the DSP block utilizes the variables which are set in the register block from the outside in the image signal processing. The control variables which are set in the register block from the outside are activated by being taken in by the processing in the DSP block to be reflected therein.
Concerning the timing for this activation, for example, there exists variables which can be activated immediately after being set in the register block, and variables which are activated synchronously with switching of a picture. A setting parameter of a synchronous signal system, an image size, an output mode, and the like are known as examples of the latter.
On the other hand, it is desired to reference the control variables generated through certain processing in the DSP block from other processing or from the outside in some cases. For example, in white balance adjustment, reference is made to an integrated value for each of the color components consisting of red (R), green (G), and blue (B) for one picture.
A set of control variables having relevance to one another in the processing in the DSP block exists in the control variables set in the register block. When any one of the variables is changed in that set, other variables of that set must also be coherently changed. The rise timing and decay timing of a horizontal synchronous signal are given as examples of such a set. Clocks specifying the two kinds of timing each are stored in two registers. The contents of the four registers in total are activated synchronously with the switching of the picture. For example, when the setting for the register is performed from host equipment (hereinafter referred to as “a host”) such as a host computer provided outside the DSP, normally this setting is performed in accordance with a sequential procedure. It therefore takes some time to perform the setting for a plurality of registers. For this reason, in order to maintain the coherency of a group of control variables having relevance to one another at the time of activation synchronized with the switching of the picture, conventionally, care needs to be taken so that a period of time required for an operation for setting a group of control variables in the register does not extend over the duration of a pulse of a vertical synchronous signal VD defining the switching of the picture. Thus, the host for performing the setting for the register must monitor the vertical synchronous signal VD. As a result, a problem is encountered where a circuit and a program become complicated in structure, and a processing load is increased.
On the other hand, even when reference is made to the control variables generated in the DSP block, the same problem arises. That is, of the control variables which are updated every picture, a group of control variables having relevance to one another need to be read out within the same picture period. For this reason, for example, the host which refers to the control variables in the DSP block needs to monitor the vertical synchronous signal VD and complete the readout operation for a period of time which does not extend over the duration of the pulse of the vertical synchronous signal VD. As a result, the problem is encountered where a circuit and a program become complicated in structure, and a processing load is increased.